1. Field of the Invention
The present invention relates in general to the effective connection between bit line sense amplifiers and data bus lines in a semiconductor memory device for securing a design margin in a cell core region and reducing a difficulty in a metal process, and more particularly to an apparatus and a method for enlarging a metal line pitch of a semiconductor memory device, in which bit line sense amplifiers are effectively connected to data bus lines to increase layout and output line pitches of a column decoder. The present apparatus and method are applicable to a very large-scale integrated memory device of the Gigabit (Gb) class to increase layout and output line pitches of a column decoder, so as to secure a margin in a metal process.
2. Description of the Prior Art
Generally, in a metal process, a resistance of a word line of poly-silicon is reduced by disposing a metal line thereon and connecting it thereto.
However, the metal line cannot secure a margin in the metal process because of a word line pitch, resulting in a considerable reduction in yield of a semiconductor memory device. In particular, a semiconductor memory device of the Gb class has a difficulty in the metal process because of reduced layout and output line pitches of a column decoder.
For this reason, a hierarchical word line structure has essentially been applied to semiconductor memory devices, beginning with a 64 Mb dynamic random access memory, to increase a metal line pitch, so as to secure a margin in the metal process.
FIG. 1 is a circuit diagram illustrating a conventional connection between bit line sense amplifiers and data bus lines in a semiconductor memory device. In this drawing, there is shown only one cell block with a cell array folded bit line structure.
In FIG. 1, a first output line of a column decoder is adapted to select four of eight bit line sense amplifiers and connect them respectively to four data bus lines. Similarly, a second output line of the column decoder is adapted to select the remaining four bit line sense amplifiers and connect them respectively to the four data bus lines. In this connection, an output line pitch of the column decoder is eight times as long as a bit line pitch.
Hence, the above-mentioned conventional construction has no particular problem in layout and output line pitches of the column decoder.
However, in a semiconductor memory device of the Gb class such as, for example, at least 4 Gb or 16 Gb, a bit line pitch is considerably reduced. For this reason, it is difficult for the above-mentioned conventional construction to be applied to the design of the column decoder and the metal process of the output lines thereof.
In other words, in the case where the above-mentioned conventional construction is applied to a very large-scale integrated memory device of the Gb class, the bit line pitch is considerably reduced, resulting in difficulties in the design of the column decoder and the metal process of the output lines thereof.